The present invention relates to a semiconductor chip, a semiconductor integrated circuit device, and a method of manufacturing semiconductor integrated circuit devices, and particularly to a technique useful for the manufacturing of nonvolatile memories of the type of block-erasure.
EE PROM of the type of electrical block erasure is a nonvolatile memory device having a function of erasing at once all memory cells or a block of memory cells formed on a semiconductor chip. The electrically block erasing EE PROM has a memory cell structure which resembles that of ordinary EPSOM. Specifically, a memory cell is formed of an insulated gate field effect transistor having a double-layer structure (will be termed xe2x80x9cMOSFETxe2x80x9d or simply xe2x80x9ctransistorxe2x80x9d), which stores data virtually in terms of the variation of threshold voltage. The data write operation of the memory cell is identical to EE PROM.
Semiconductor integrated circuit devices including the above-mentioned nonvolatile memory cells are designed to have individual operating voltages depending on their application systems even though the internal circuit arrangement is common. For example, integrated circuit devices used in personal computer systems operate at such a relatively high voltage as 3.0 V, those used in portable terminal units operate at such an intermediate voltage as 2.5 V, and those mounted on FIC cards operate at such a low voltage as 1.8 V. Due to different types of semiconductor integrated circuit devices, which are identical in internal memory structure but different in operating voltage, the production efficiency is deteriorated.
The inventors of the present invention have contemplated the enhancement of production efficiency of semiconductor integrated circuit devices, which is based on the formation of memory cell arrays and their selection circuits in a common circuit arrangement operative at several operating voltages and the formation of voltage-dependent circuits which fit individual operating voltages, with one circuit being made operative at its operating voltage in the manner of bonding or the like.
The present inventors also have noted that among semiconductor integrated circuits of MOSFET, etc. Designed to fit several operation voltages, the worst condition in achieving the same performance, e.g., operation speed, is the lowest operating voltage, and thought of the expanded application of this idea to the enhancement of the yield of products and the rational demand-responsive production management in consideration of the operating voltage.
Accordingly, it is an object of the present invention to provide a semiconductor chip which is uniquely value-added.
Another object of the present invention is to provide a semiconductor integrated circuit device which improves the productivity and yield of products, and facilitates the production management.
Still another object of the present invention is to provide a method of manufacturing semiconductor integrated circuit devices which enables the enhancement of productivity and yield of products and the rational demand-responsive production management.
These and other objects and novel features of the present invention will be apparent from the following description and accompanying drawings.
Among the affairs of the present invention disclosed in this patent application, a representative is briefed as follows.
The inventive semiconductor chip is arranged to include a common circuit block which is operative at a first voltage and a second voltage that is higher than the first voltage, a first circuit block which is designed to fit the first voltage and operate in unison with the common circuit block, a second circuit block which is designed to fit the second voltage and operate in unison with the common circuit block, and a voltage type setup circuit which activates one of the first and second circuit blocks, with a first identification record indicative of the operability at the first voltage or a second identification record indicative of the operability only at the second voltage being held by the chip.
Another representative disclosed in this patent application is briefed as follows.
The inventive semiconductor integrated circuit device is arranged in a semiconductor chip, which include a common circuit block which is operative at a first voltage and a second voltage that is higher than the first voltage, a first circuit block which is designed to fit the first voltage and operate in unison with the common circuit block, a second circuit block which is designed to fit the second voltage and operate in unison with the common circuit block, and a voltage type setup circuit which activates one of first and second circuit blocks, the voltage type setup circuit selecting the first or second circuit block if the chip is operative at the first voltage or selecting the second circuit block if the chip is operative only at the second voltage.
Still another representative disclosed in this patent application is briefed as follows.
The inventive method of manufacturing semiconductor integrated circuit devices includes the steps of forming semiconductor chips on a wafer, each chip including a common circuit block which is operative at a first voltage and a second voltage that is higher than the first voltage, a first circuit block which is designed to fit the first voltage and operate in unison with the common circuit block, a second circuit block which is designed to fit the second voltage and operate in unison with the common circuit block, and a voltage type setup circuit which activates one of first and second circuit blocks, testing the operability of each chip at the first and second voltages during the probing test process, setting up the first voltage to the voltage type setup circuit in the assembly process for a chip which is operative at the first voltage, and setting up the second voltage to the voltage type setup circuit during the assembly process for a chip which is operative at the first voltage and for a chip which is operative only at the second voltage in accordance with the test result and the demand of products.